index - Equipe Secure and Safe Hardware

 

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Mots clés

Reliability Simulation Cryptography Machine learning Reverse-engineering Intrusion detection Security and privacy Side-channel analysis Internet of Things Formal methods Power-constant logic Side-Channel Analysis SCA Power demand Estimation DRAM Writing Side-channel attack Field programmable gate arrays Protocols Mutual Information Analysis MIA Field Programmable Gates Array FPGA Reverse engineering Coq Temperature sensors Fault injection Elliptic curve cryptography Side-Channel Attacks MRAM Process variation Electromagnetic Filtering TRNG Magnetic tunnel junction Routing Resistance Masking countermeasure Transistors Dual-rail with Precharge Logic DPL Fault injection attack Energy consumption FPGA Logic gates Computational modeling Confusion coefficient Hardware RSA Switches Costs Image processing Signal processing algorithms PUF Defect modeling Training Randomness STT-MRAM GSM Fault attacks Lightweight cryptography Authentication Masking SoC Gem5 Random access memory Loop PUF CRT Magnetic tunneling Security services Neural networks Application-specific VLSI designs Hardware security Side-Channel Analysis AES Dynamic range Convolution Voltage Differential power analysis DPA Information leakage 3G mobile communication Sensors EMFI Linearity Memory Controller Countermeasures OCaml Robustness Side-channel attacks SCA Countermeasure Formal proof Receivers SCA Side-channel attacks Aging CPA Security FDSOI Circuit faults Spin transfer torque ASIC Asynchronous Differential Power Analysis DPA

 

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217

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Open access

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